1. Field of the Invention
Embodiments of the present invention relate to reconfigurable computing architectures. More particularly, embodiments of the present invention relate to reconfigurable computing architectures that allow a plurality of processing elements to communicate with a plurality of memory elements.
2. Description of the Related Art
Computing architectures, particularly for digital signal processing (DSP) and high-performance computing (HPC), typically include a processing element coupled to a memory element and often include a plurality of processing elements accessing a plurality of memory elements. The communication architecture between the processors and the memory may include a switching element, such as a crossbar switch. While the switch may be programmable, in that any input may be routed to any output, the switch often comprises static switching elements that are not reconfigurable. Furthermore, the processor-switch-memory architecture may not be flexible to accommodate variations in the types of processor or memory elements that are utilized in the architecture. The processing and memory elements may not be capable of executing more than one type of application, particularly executing more than one type of application simultaneously.